Layout versus schematic (LVS) comparison is a fundamental step in IC design verification. It involves verifying that the physical layout of the circuit matches its schematic representation, ensuring correctness and functionality. This step is critical for ensuring the functionality and reliability of integrated circuits (ICs). Traditionally, designers perform LVS comparison during signoff verification using dedicated tools that compare layout and schematic data, identifying any inconsistencies or errors. However, uncovering errors at the signoff stage leads to time-consuming iterations that delay design closure and time to market. Performing LVS earlier in the design flow is now essential due to the high number of violations that occur because of the incomplete status of the design.

The Calibre nmLVS™ Recon solution delivers an intelligent shift-left process for fast and precise LVS verification earlier in the design cycle. Calibre nmLVS Recon flow include short path isolation with Calibre nmLVS Recon SI, soft connection conflicts and electrical rule checks with Calibre nmLVS Recon ERC [3] and early-stage circuit/layout comparison with the Calibre nmLVS Recon Compare.

In this webinar, we will discuss the different features of the three components of LVS Recon flow demonstrating their high value for customers in cutting down their tape out cycle.