Effective Monitoring, Test, and Repair of Multi-Die Designs

Topics Covered
  • Motivation for Multi-Die Designs
  • Challenges in Testing Multi-Die Designs
  • The Synopsys Multi-Die Test Solution
  • Synopsys Solutions for IEEE1838 and Lane Test and Repair (LTR)
  • Synopsys ext-RAM and UCIe Monitor, Test, and Repair (MTR) IP

White Paper Overview 

Despite the clear advantages of multi-die designs, there are numerous new challenges that stand in the way of multi-die design realization. This white paper focuses on the test challenges of multi-die designs for chiplets (pre-bond), interconnects (mid/post-bond), and multi-die stacks/packages (post pond). Overcome such challenges with Synopsys’ comprehensive multi-die solutions for testing and repair of different types of die-to-die interfaces and lanes. The solutions test for and diagnose known-good stacks and known-good dies, support extensive BIST capabilities, and offer in-field interconnect monitoring for purposes such as predictive maintenance.

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